Optical lithography nowadays often uses wavelengths of 248 nm or 193 nm. With 193 nm immersion lithography integrated circuit (IC) manufacturing is possible down to the 45 nm node or even down to the 32 nm node. However, for printing in sub-32 nm half pitch node, 193 nm is probably not satisfactory due to theoretical limitations, unless double patterning is used. Instead of using wavelengths of 193 nm, a more advanced technology has been introduced, also referred to as extreme ultraviolet lithography (EUV lithography), which uses wavelengths of 10 nm to 14 nm, with as typical value 13.5 nm. This technique was previously also known as soft X-ray lithography more specifically using wavelengths in the range of 2 nm to 50 nm.
Over the past years a tremendous effort has been put on Extreme Ultraviolet lithography (EUVL) for printing lines with pitches below 60 nm. Optimization of EUV lithography has included optimization of mask, illumination techniques, treatments and photoresists used. The particular EUV Photo Resist (PR) that has been selected for EUV processing has different etch resistivity and thickness compared to a 193(i) photoresist (193 immersion photoresist), bringing new challenges for dry etching.
One drawback of EUV lithography is the photoresist height which is typically reduced after exposure down to about 50 nm. FIG. 1 shows the evolution of the lithography stack thickness after spin coating (nominal thickness) (A) and after exposure (B), whereby for larger pitches the results for 193 nm immersion lithography are shown and for smaller pitches the results for a typical EUV lithography process as currently used are shown. The thickness for the stack in 193 nm immersion lithography is determined by the thickness of the BARC (bottom anti-reflective coating) and the thickness of the photoresist, whereas for a EUV lithography the stack thickness is determined based on the thickness of the under layer (UL) and the thickness of the photoresist.
An example of a typical stack used in EUV lithographic processing is schematically illustrated in FIG. 2. The stack typically comprises a silicon on insulator (SOI) wafer with a buried oxide layer (BOX) 102, a crystalline silicon layer (C—Si) 104, a set of two hardmask layers 106, 108, an underlayer (UL) 110, and an EUV photoresist layer 112.
In FIG. 1, it can be observed that as the device pitch is scaled down, the photoresist budget—being the amount of photoresist thickness that is left for protecting the underlying layers during and after processing—is dramatically reduced.
The reduction of the photoresist height can amongst others also be caused by the application of a hydrogen H2 pre-plasma-treatment (PPT), which consumes the photoresist. Nevertheless, such a pre-plasma-treatment is interesting as it significantly improves the line width roughness (LWR) for the lithographic processed device and, therefore, preferably is applied.
Another cause of the reduction of the photoresist is the need for hard mask opening, e.g., obtained through dry etching. The ion bombardment and VUV photons used degrades the photoresist, and as a consequence thereof also degrades the line width roughness that is finally obtained.
Due to the drastic reduction of the photoresist height a too narrow process window for further etching steps typically is created. With the need for smaller device pitches, there is therefore a need for improving the photoresist etch resistivity, as for the smallest pitches of interest, the photoresist etch resistivity is too low to provide appropriate lithographic processing. Therefore, there is room for improving EUV lithographic processing, bearing in mind that currently the EUV photoresist height and the etch resistivity are so low when small pitches need to be processed.